The project

I wanted to learn a bit more about digital design and computer architecture, and what better way is there besides making your own CPU?

A Central Processing Unit (CPU) is a unit that processes centrals. CPUs are often categorised by their instruction set architecture (ISA), the most common ones are ARM, RISC-V, and the older x86-64. In the 2000s they decided to use the alphabet to name new ISAs.

RISC-V is an acronym for RISC Instruction Set Computer-V (no idea what the V stands for, maybe vacuous) is a free and open standard ISA. I thought this might be a good choice for learning. It will be a single-cycle CPU, which means it will be super slow, because the clock period has to be as long as the slowest instruction. This is for simplicity's sake.

Writing hardware

How do you "make" a CPU? You write it in software hardware.

Hardware description languages (HDL) are computer languages made for describing electronic circuits. The most insufferable one is VHDL (Very Descriptive Hardware Language), which, as the name implies, is a strongly typed language. Like other HDLs, it is a dataflow language, which means it can be used to describe concurrent systems (C developers cope and seethe). It is the most infuriating language ever. It is case-insensitive, but for some reason, VHDL people love to capitalise random letters. It is the only language where you'll get a syntax error for inserting a missing semicolon.

I hate this language

Why do I need to put end process to close a process block, when I can just write end to end an architecture block?

VHDL doesn't even have 64-bit integers.

enif

Why is it elsif? Don't tell me the Verbose Hardware Description Lanugage can't spare two extra characters to make it else if.

I wish this was harder

Surely there is a better way to describe hardware? This is where the type theorists come out of the woodwork to tell you about Clash.

The ALU and ALUI

All Logic is Unsigned (ALU) is the mindset. The DoD boomers who made this language want to brainwash you into thinking doing this to a logic vector is normal: to_integer(unsigned(sig)).

Never touch std_logic_vector.

Return from digression

I recently "finished" the ALU. The register file and data memory is still being worked on.

I use GHDL to analyse, compile and simulate VHDL, and GTKWave to view waveforms and timing.

Source code repository

The source code is available at https://codeberg.org/ove/riscv-cpu.

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